The present invention relates to a configuration and a method for the simultaneous switching of a transistor in the on state to the off state and of a transistor connected in series therewith and in the off state to the on state.
A circuit that contains two transistors to be so operated is shown in FIG. 5.
The circuit shown includes a PMOS transistor P and an NMOS transistor N connected in series therewith. The transistor P is connected to the first terminal hSup of a supply voltage. The transistor N is connected to the second terminal lSup of the supply voltage. The gate terminals of the transistors P and N are connected to a digital input signal DIGIN of the configuration and a digital output signal DIGOUT is tapped off from the configuration between the transistors P and N.
Of the transistors P and N, regardless of the level of the input signal DIGIN, in each case one of the transistors is on and the respective other transistor is off.
In the event of a change in the level of the input signal DIGIN, the transistor in the on state is changed to the off state, and the transistor in the off state is changed to the on state.
Such a configuration is used, for example, in an inverter.
Existing problems of such configurations lie in the fact that, during the simultaneous switching of the transistors, there is a phase during which both transistors are on. In such a phase, the first terminal hSup and the second terminal lSup of the supply voltage are short-circuited through the transistors P and N.
Such a condition is disadvantageous for various reasons. In particular, a very high current flows in the short-circuit phases:
which leads to severe heating of the configuration and can even destroy the transistors P and N; and
which can have the consequence that, on parasitic inductances that are present in series with the transistors P and N, considerable voltages may drop, because of the large di/dt, which results in considerable disruption to the output signal DIGOUT, in particular, in the case of switching operations that follow one another rapidly.
There already exist a large number of proposals in the prior art for the elimination of the aforementioned problems. However, such proposals can be implemented only with a great outlay and/or are not able to eliminate the aforementioned problems satisfactorily.
It is accordingly an object of the invention to provide a configuration and method for switching transistors that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that, in a simple manner, reliably and without accepting other disadvantages, prevents short circuits from occurring when switching the transistors.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a circuit configuration for a simultaneous switching of transistors, including first and second transistors connected in series, each of the transistors having a gate terminal with a gate potential, an on state, and an off state, and the transistors respectively switching one of from the on state to the off state in an off transition and from the off state to the on state in an on transition, and when the transistors are switched, the gate potential of one of the transistors performing the on transition being changed slower than the gate potential of another of the transistors performing the off transition.
With the objects of the invention in view, there is also provided a method for simultaneously switching transistors, including the steps of respectively switching first and second transistors connected in series one of from an on state to an off state in an off transition and from the off state to the on state in an on transition, with a gate potential of one of the transistors performing the on transition being changed slower than a gate potential of another of the transistors performing the off transition.
The configuration and method according to the invention are distinguished by the fact that they ensure that, when the transistors are switched from the on state to the off state or from the off state to the on state, the gate potential of the transistor that is changed from the off state to the on state by the switching operation changes more slowly than the gate potential of the transistor that is changed from the on state to the off state by the switching operation.
As a result, the transistor that was originally off can only pass into the on state when the originally on transistor is no longer in the completely turned-on state, even in the case in which the switching of the transistors is started at the same time. The result of such a configuration is that, at no time can both transistors simultaneously be in the fully on state; during the switching operation, at least one of the transistors is in a state in which it acts as a current source that limits the current flow through the transistors.
By the claimed configuration and the claimed method, it is consequently possible, in a simple way, reliably and without accepting other disadvantages, to prevent short-circuits from occurring when switching the transistors.
In accordance with another feature of the invention, when the transistors are switched one of from the on state to the off state and from the off state to the on state, the gate potentials of the transistors are ensured to begin to change simultaneously.
In accordance with a further feature of the invention, there is provided a driving configuration connected to the transistors, the driving configuration, during switching of the transistors, driving the transistors to cause at least one of the transistors to act as a current source limiting current flow through the transistors in phases during which neither of the transistors is in the off state.
In accordance with an added feature of the invention, one of the transistors is a PMOS transistor, and another of the transistors is an NMOS transistor.
In accordance with an additional feature of the invention, each of the transistors has a source terminal, the source terminal of the first transistor is to be connected to a first terminal of a supply voltage, and the source terminal of the second transistor is to be connected to a second terminal of the supply voltage.
In accordance with yet another feature of the invention, one of the on state and the off state of a respective one of the transistors is to be dependent upon an input signal and the input signal does not drive the transistors.
In accordance with yet a further feature of the invention, there is provided a first supply voltage terminal, a second supply voltage terminal, a first additional transistor, a second additional transistor, the gate terminal of the first transistor connected through the first additional transistor to the first supply voltage terminal, and the gate terminal of the second transistor connected through the second additional transistor to the second supply voltage terminal.
In accordance with yet an added feature of the invention, each of the first and second additional transistors have a gate terminal, an on state, and an off state, and the gate terminals of the first and second additional transistors are to be driven respectively in one of the on state and the off state.
In accordance with yet an additional feature of the invention, the gate terminals of the additional transistors are to be driven by one of an input signal and a signal based upon the input signal.
In accordance with again another feature of the invention, there is provided a third additional transistor to be driven as a function of a voltage between the first and second transistors and an input signal, and the gate terminal of the first transistor connected through the third additional transistor to the first voltage supply terminal.
In accordance with again a further feature of the invention, there is provided a fourth additional transistor to be driven as a function of a voltage present on the gate terminal of the second transistor and the input signal, and the gate terminal of the first transistor connected through the fourth additional transistor to the first voltage supply terminal.
In accordance with again an added feature of the invention, there is provided a fifth additional transistor to be driven as a function of a voltage between the first and second transistors and the input signal, and the gate terminal of the second transistor connected through the fifth additional transistor to the second voltage supply terminal.
In accordance with again an additional feature of the invention, there is provided a sixth additional transistor to be driven as a function of a voltage present on the gate terminal of the first transistor and the input signal, and the gate terminal of the second transistor connected through the sixth additional transistor to the second voltage supply terminal.
In accordance with still another feature of the invention, the gate terminal of the first transistor and the gate terminal of the second transistor are connected through at least one resistive element, preferably, a transistor.
In accordance with a concomitant feature of the invention, the at least one resistive element is to be driven by a bias current.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a configuration and method for switching transistors, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.